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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8343 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-470 0 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dc-to-2.5 ghz high ip3 active mixer functional block diagram 14 13 12 11 10 9 8 1 2 3 4 5 6 7 bias comm AD8343 inpp inpm dcpl vpos pwdn comm comm outp outm comm loip loim comm features high-performance active mixer broadband operation to 2.5 ghz conversion gain: 7.1 db input ip3: 16.5 dbm lo drive: C10 dbm noise figure: 14.1 db input p1 db: 2.8 dbm differential lo, if and rf ports 50 lo input impedance single-supply operation: 5 v @ 50 ma typical power-down mode @ 20 a typical applications cellular base stations wireless lan satellite converters sonet/sdh radio radio links rf instrumentation product description the AD8343 is a high-performance broadband active mixer. having wide bandwidth on all ports and very low intermodulation distortion, the AD8343 is well suited for demanding transmit or receive channel applications. the AD8343 provides a typical conversion gain of 7.1 db. the integrated lo driver supports a 50 ? differential input imped- ance with low lo drive level, helping to minimize external component count. the open-emitter differential inputs may be interfaced directly to a differential filter or driven through a balun (transformer) to provide a balanced drive from a single-ended source. the open-collector differential outputs may be used to drive a differ ential if signal interface or convert to a single-ended signal through the use of a matching network or transformer. when cen- tered on the vpos supply voltage, the outputs may swing 1v. the lo driver circuitry typically consumes 15 ma of current. two external resistors are used to set the mixer core current for required performance resulting in a total current of 20 ma to 60 ma. this corresponds to power consumption of 100 mw to 300 mw with a single 5 v supply. the AD8343 is fabricated on analog devices proprietary, high-performance 25 ghz silicon bipolar ic process. the AD8343 is available in a 14-lead tssop package. it operates over a C 40 c to +85 c temperature range. a device-populated evaluation board is available to facilitate device matching.
rev. a C2C AD8343?pecifications basic operating conditions parameter conditions figure min typ max unit input interface (inpp, inpm) differential open emitter dc bias voltage internally generated 1.1 1.2 1.3 v operating current each input (i o ) current set by r3, r4 24 5 16 20 ma value of bias setting resistor 1 1% bias resistors; r3, r4 24 68.1 ? port differential impedance f = 50 mhz; r3 and r4 = 68.1 ? 9 2.7 + j 6.8 ? output interface (outp, outm) differential open collector dc bias voltage externally applied 4.5 5 5.5 v voltage swing 1.65 v s 1v s + 2 v operating current each output same as input current i o ma port differential impedance f = 50 mhz 12 900 C j77 ? lo interface (loip, loim) differential common base stage dc bias voltage 2 internally generated; port 300 360 450 mv typically ac-coupled lo input power 50 ? impedance 17 C 12 C 10 C 3 dbm port differential return loss 16 C 10 db power-down interface (pwdn) pwdn threshold assured on v s C 1.5 v assured off v s C 0.5 v pwdn response time 3 time from device on to off 4 2.2 s time from device off to on 5 500 ns pwdn input bias current pwdn = 0 v (device on) C 85 C 195 a pwdn = 5 v (device off) 0 a power supply supply voltage range 4.5 5.0 5.5 v total quiescent current r3 and r4 = 68.1 ? 24 50 60 ma over temperature 75 ma powered-down current v s = 5.5 v 20 95 a v s = 4.5 v 6 15 a over temperature, v s = 5.5 v 50 150 a notes 1 the balance in the bias current in the two legs of the mixer input may be important in applications where a low feedthrough of the local oscillator (lo) is critical. 2 this voltage is proportional to absolute temperature (ptat). reference section on dc-coupling the lo for more information regar ding this interface. 3 response time until device meets all specified conditions. specifications subject to change without notice. (v s = 5.0 v, t a = 25 c)
rev. a AD8343 C3C table i. typical ac performance (v s = 5.0 v, t a = 25 c; see figure 24 and tables iii through v.) input 1 db input frequency output frequency conversion gain ssb noise figure input ip3 compression point (mhz) (mhz) (db) (db) (dbm) (dbm) receiver characteristics 400 70 5.6 10.5 20.5 3.3 900 170 3.6 11.4 19.4 3.6 1900 170 7.1 14.1 16.5 2.8 2400 170 6.8 15.3 14.5 2.1 2400 425 5.4 16.2 16.5 2.2 transmitter characteristics 150 900 7.5 17.9 18.1 1.9 150 1900 0.25 16.0 13.4 0.8 table ii. typical isolation performance (v s = 5.0 v, t a = 25 c; see figure 24 and tables iii through v.) input frequency output frequency lo to output 2 lo to output 3 lo to output input to output (mhz) (mhz) leakage (dbm) leakage (dbm) leakage (dbm) leakage (dbm) receiver characteristics 400 70 C 40.1 C 51.0 C 44.0 C 62.4 900 170 C 44.4 C 35.5 < C 75.0 C 56.9 1900 170 C 65.6 C 38.3 C 73.3 C 65.7 2400 170 C 66.7 C 44.4 < C 75.0 C 73.7 2400 425 C 51.1 C 49.4 < C 75.0 C 52.3 transmitter characteristics 150 900 C 27.6 < C 75 dbm < C 75 dbm C 35.3 150 1900 < C 75 dbm < C 75 dbm < C 75 dbm C 69.7 low-side lo injection used for typical performance. absolute maximum ratings 1 vpos quiescent voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v outp, outm quiescent voltage . . . . . . . . . . . . . . . . 5.5 v inpp, inpm voltage differential . . . . . . . . . . . . . . . 500 mv loip, loim current (injection or extraction) . . . . . . 1 ma loip, loim voltage differential . . . . . . . . . . . . . . . 500 mv internal power dissipation (tssop) 2 . . . . . . . . . . . . 320 mw ja (tssop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 c/w maximum junction temperature . . . . . . . . . . . . . . . . . 125 c operating temperature range . . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . . C 65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 a portion of the device power is dissipated by the external bias resistors r3 and r4. ordering guide temperature package package model range description option AD8343aru ru-14 AD8343aru-reel C 40 c to 14-lead 13" tape +85 c plastic and reel tssop AD8343aru-reel7 7" tape and reel AD8343-eval evaluation board pin configuration top view (not to scale) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 comm AD8343 inpp inpm dcpl vpos pwdn comm comm outp outm comm loip loim comm
C4C rev. a AD8343 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8343 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions tssop name function simplified interface schematic 2, 3 inpp/inpm differential input pins. need to be dc-biased; typically ac-coupled. 12, 13 outp/outm open collector differential output pins. need to be dc-biased and ac-coupled. 9, 10 loip/loim differential local oscillator (lo) input pins. typically ac-coupled. 6 pwdn power-down interface. connect pin to ground for normal operating mode. connect pin to supply for power-down mode. 4 dcpl bias rail decoupling capacitor connection for lo driver. 5 vpos positive supply voltage (v s ), 4.5 v to 5.5 v. ensure adequate supply bypassing for proper device operation as shown in figure 24. 1, 7, 8, comm connect to low impedance circuit ground. 11, 14 vpos 5v dc loip loim outp 5v dc outm 5v dc inpp inpm vpos 5v dc 1.2v dc 1.2v dc vpos 5v dc loip loim 400 vbias 360mv dc 360mv dc 400 vpos 5v dc pwdn 25k bias cell to mixer core r1 10 dcpl vpos loip loim 2v dc 360mv dc 360mv dc bias cell lo buffer
rev. a conversion gain ?db 60 0 5.37 percentage 50 40 30 20 10 mean: 5.57db 5.42 5.47 5.52 5.57 5.62 5.67 5.72 tpc 1. gain histogram f in = 400 mhz, f out = 70 mhz input 1db compression point dbm 45 0 3.24 percentage 40 35 30 25 20 15 10 5 mean: 3.31dbm 60 55 50 3.26 3.28 3.30 3.32 3.34 3.36 3.38 tpc 2. input ip3 histogram f in = 400 mhz, f out = 70 mhz input 1db compression point dbm 45 0 3.24 percentage 40 35 30 25 20 15 10 5 mean: 3.31dbm 60 55 50 3.26 3.28 3.30 3.32 3.34 3.36 3.38 tpc 3. input 1 db compression point histogram f in = 400 mhz, f out = 70 mhz temperature c 10 4 40 conversion gain db 9 8 7 6 5 0 20406080 20 tpc 4. gain performance over temperature f in = 400 mhz, f out = 70 mhz temperature c 24 40 input ip3 dbm 22 21 20 19 18 0 20406080 20 17 16 15 23 tpc 5. input ip3 performance over temperature f in = 400 mhz, f out = 70 mhz temperature c 5.0 2.0 40 input 1db compression point dbm 4.5 4.0 3.5 3.0 2.5 0 20406080 20 tpc 6. input 1 db compression point performance over temperature (f in = 400 mhz, f out = 70 mhz) typical performance characteristics AD8343 C5C receiver characteristics (f in = 400 mhz, f out = 70 mhz, f lo = 330 mhz [figure 24, tables iii and iv])
C6C rev. a AD8343 receiver characteristics (f in = 900 mhz, f out = 170 mhz, f lo = 730 mhz [figure 24, tables iii and iv]) conversion gain db 0 3.45 percentage 35 30 25 20 15 10 5 mean: 3.63db 3.40 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85 tpc 7. gain histogram f in = 900 mhz, f out = 170 mhz 20.4 input ip3 dbm 0 18.2 percentage 30 20 10 2 mean: 19.4dbm 8 6 4 12 14 16 18 22 24 26 28 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 tpc 8. input ip3 histogram f in = 900 mhz, f out = 170 mhz input 1db compression point dbm 30 0 3.52 percentage 28 26 24 22 20 2 mean: 3.62dbm 18 16 14 12 10 9 6 4 3.54 3.56 3.58 3.60 3.62 3.64 3.66 3.68 3.70 3.72 tpc 9. input 1 db compression point histogram f in = 900 mhz, f out = 170 mhz temperature c 6 0 40 conversion gain db 5 4 3 2 1 0 20406080 20 tpc 10. gain performance over temperature f in = 900 mhz, f out = 170 mhz temperature c 23 15 40 input ip3 dbm 22 21 20 19 16 0 20406080 20 18 17 tpc 11. input ip3 performance over temperature f in = 900 mhz, f out = 170 mhz temperature c 5.0 2.0 40 input 1db compression point dbm 4.5 4.0 3.5 3.0 2.5 0 20406080 20 tpc 12. input 1 db compression point performance over temperature f in = 900 mhz, f out = 170 mhz
rev. a AD8343 C7C receiver characteristics (f in = 1900 mhz, f out = 170 mhz, f lo = 1730 mhz [figure 24, tables iii and iv]) conversion gain db 0 6.80 percentage 28 26 24 22 20 10 2 6.75 4 6 8 18 16 14 12 6.90 6.85 7.00 6.95 7.10 7.05 7.20 7.15 7.30 7.25 mean: 7.09db tpc 13. gain histogram f in = 1900 mhz, f out = 170 mhz 18.5 input ip3 dbm 0 14.0 percentage 45 10 5 15 20 25 30 35 40 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 mean: 16.54dbm tpc 14. input ip3 histogram f in = 1900 mhz, f out = 170 mhz input 1db compression point dbm 50 0 2.60 percentage 45 40 35 30 25 5 20 15 10 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 mean: 2.8dbm tpc 15. input 1 db compression point histogram f in = 1900 mhz, f out = 170 mhz temperature c 10 4 40 conversion gain db 9 8 7 6 5 0 20406080 20 %&'(3 )&

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C8C rev. a AD8343 receiver characteristics (f in = 2400 mhz, f out = 170 mhz, f lo = 2230 mhz [figure 24, tables iii and iv]) conversion gain db 0 6.0 percentage 40 35 30 20 15 10 5 5.8 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 25 mean: 6.79db tpc 19. gain histogram f in = 2400 mhz, f out = 170 mhz input ip3 dbm 0 13.0 percentage 35 25 10 5 15 20 30 13.2 13.4 13.6 13.8 14.0 14.2 14.4 14.6 14.8 15.0 15.2 15.4 15.6 mean: 14.46dbm tpc 20. input ip3 histogram f in = 2400 mhz, f out = 170 mhz input 1db compression point dbm 45 0 1.90 percentage 40 35 30 25 20 15 10 5 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 input: 2.11dbm tpc 21. input 1 db compression point histogram f in = 2400 mhz, f out = 170 mhz temperature c 10 4 40 conversion gain db 9 8 7 6 5 0 20406080 20 tpc 22. gain performance over temperature f in = 2400 mhz, f out = 170 mhz temperature c 18 40 input ip3 dbm 17 16 15 14 13 0 20406080 20 12 11 10 tpc 23. input ip3 performance over temperature f in = 2400 mhz, f out = 170 mhz temperature c 3.0 0 40 input 1db compression point dbm 2.5 2.0 1.5 1.0 0.5 0 20406080 20 tpc 24. input 1 db compression point performance over temperature f in = 2400 mhz, f out = 170 mhz
rev. a AD8343 C9C receiver characteristics (f in = 2400 mhz, f out = 425 mhz, f lo = 1975 mhz [figure 24, tables iii and iv]) conversion gain db 0 4.4 percentage 24 22 20 18 16 14 2 4.2 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.6 12 10 8 6 4 6.2 6.4 mean: 5.40db tpc 25. gain histogram f in = 2400 mhz, f out = 425 mhz input ip3 dbm 0 14.2 percentage 22 12 2 8 6 4 10 14 16 18 20 15.4 15.6 15.8 16.0 16.2 16.4 16.6 16.8 17.2 17.4 17.6 17.8 mean: 16.50dbm 17.0 18.0 15.2 15.0 tpc 26. input ip3 histogram f in = 2400 mhz, f out = 425 mhz mean: 2.22dbm input 1db compression point dbm 0 2.05 percentage 65 60 55 50 45 40 5 2.00 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 35 30 25 20 15 10 tpc 27. input 1 db compression point histogram f in = 2400 mhz, f out = 425 mhz temperature c 10 4 40 conversion gain db 9 8 7 6 5 0 20406080 20 %&'"7 )&

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C10C rev. a AD8343 transmit characteristics (f in = 150 mhz, f out = 900 mhz, f lo = 750 mhz [figure 24, tables iii and iv]) conversion gain db 0 7.20 percentage 35 30 25 20 15 10 5 7.70 mean: 7.49db 7.25 7.30 7.35 7.40 7.45 7.50 7.55 7.60 7.65 u tpc 31. gain histogram f in = 150 mhz, f out = 900 mhz input ip3 dbm 24 0 percentage 22 20 18 16 14 12 10 2 mean: 18.1dbm 17.85 17.8 4 6 8 17.9 17.95 18.0 18.05 18.1 18.15 18.2 18.25 18.3 18.35 18.4 18.45 tpc 32. input ip3 histogram f in = 150 mhz, f out = 900 mhz input 1db compression point dbm 24 0 percentage 22 20 18 16 14 12 10 2 mean: 1.9dbm 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 1.55 4 6 8 tpc 33. input 1 db compression point histogram f in = 150 mhz, f out = 900 mhz temperature c 10 4 40 conversion gain db 9 8 7 6 5 0 20406080 20 tpc 34. gain performance over temperature f in = 150 mhz, f out = 900 mhz temperature c 20 40 input ip3 dbm 19 18 17 16 15 0 20406080 20 14 13 12 tpc 35. input ip3 performance over temperature f in = 150 mhz, f out = 900 mhz temperature c 3.0 0.0 40 input 1db compression point dbm 2.5 2.0 1.5 1.0 0.5 0 20406080 20 tpc 36. input 1 db compression point performance over temperature f in = 150 mhz, f out = 900 mhz
rev. a AD8343 C11C transmit characteristics (f in = 150 mhz, f out = 1900 mhz, f lo = 1750 mhz [figure 24, tables iii and iv]) conversion gain db 0 1.0 0.8 percentage 40 35 30 25 20 15 10 5 mean: 0.25db 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 tpc 37. gain histogram f in = 150 mhz, f out = 1900 mhz input ip3 dbm 45 0 10.5 percentage 40 35 30 25 20 15 10 5 mean: 13.4dbm 50 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 tpc 38. input ip3 histogram f in = 150 mhz, f out = 1900 mhz input 1db compression point dbm 45 0 1 0.5 percentage 40 35 30 25 20 15 10 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 mean: 0.79dbm tpc 39. input 1 db compression point histogram f in = 150 mhz, f out = 1900 mhz temperature c 5 2 40 conversion gain db 3 2 1 0 1 0 20406080 20 4 %&'$+ )&

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C12C rev. a AD8343 circuit description the AD8343 is a mixer intended for high-intercept applications. the signal paths are entirely differential and dc-coupled to permit high-performance operation over a broad range of frequencies; the block diagram (figure 1) shows the basic functional blocks. the bias cell provides a ptat (proportional to absolute temperature) bias to the lo driver and core. the lo driver consists of a three-stage limiting differential amplifier that provides a very fast (almost square-wave) drive to the bases of the core transistors. the AD8343 core utilizes a standard architecture in which the signal inputs are directly applied to the emitters of the transistors in the cell (figure 7). the bases are driven by the hard-limited lo signal that directs the transistors to steer the input currents into periodically alternating pairs of output terminals, thus providing the periodic polarity reversal that effectively multiplies the signal by a square wave of the lo frequency. bias AD8343 vpos dcpl pwdn loip loim inpp inpm outp outm comm mixer core lo driver q1 q2 q3 q4 figure 1. topology to illustrate this functionality, when loip is positive, q1 and q4 are turned on, and q2 and q3 are turned off. in this condition q1 connects i inpp to outm and q4 connects i inpm to outp. when loip is negative the roles of the transistors reverse, steering i inpp to outp and i inpm to outm. isolation and gain are possible because at any instant the signal passes through a common-base transistor amplifier pair. multiplication is the essence of frequency mixing; an ideal multi- plier would make an excellent mixer. the theory is expressed in the following trigonometric iden tity: sin ( sig t ) sin ( lo t ) = 1/2 [ cos ( sig t ? lo t ) C cos ( sig t + lo t )] this states that the product of two sine-wave signals of different frequencies is a pair of sine waves at frequencies equal to the sum and difference of the two frequencies being multiplied. unfortunately, practical implementations of analog multipliers generally make poor mixers because of imperfect linearity and the added noise that invariably accompanies attempts to improve lin- earity. the best mixers to date have proven to be those that use the lo signal to periodically reverse the polarity of the input signal. in this class of mixers, frequency conversion occurs as a result of multiplication of the signal by a square wave at the lo frequency. because a square wave contains odd harmonics in addition to the fundamental, the signal is effectively multiplied by each frequency component of the lo. the output of the mixer will therefore contain signals at f lo f sig , 3 f lo f sig , 5 f lo f sig , and 7 f lo f sig . the amplitude of the compo- nents arising from signal multiplication by lo harmonics falls off with increasing harmonic order because the amplitude of a square wave s harmonics falls off. an example of this process is illustrated in figure 2. the first pane of this figure shows an 800 mhz sinusoid intended to represent an input signal. the second pane contains a square wave repre- senting an lo signal at 600 mhz which has been hard-limited by the internal lo driver. the third pane shows the time domain representation of the output waveform and the fourth pane shows the frequency domain representation. the two strongest lines in the spectrum are the sum and difference frequencies arising from multiplication of the signal by the lo s fundamental frequency. the weaker spectral lines are the result of the multiplication of the signal by various harmonics of the lo square wave. frequency domain local oscillator time domain signal sig lo sig lo frequency sig lo sig lo 3 lo sig 5 lo sig 3 lo sig 7 lo sig 5 lo sig figure 2. signal switching characteristics of the AD8343
rev. a AD8343 C13C dc interfaces biasing and decoupling (vpos, dcpl) vpos is the power supply connection for the internal bias cir- cuit and the lo driver. this pin should be closely bypassed to gnd with a capacitor in the range of 0.01 f to 0.1 f. the dcpl pin provides access to an internal bias node for noise bypassing purposes. this node should be bypassed to comm with 0.1 f. power-down interface (pwdn) the AD8343 is active when the pwdn pin is held low; other- wise the device enters a low-power state as shown in figure 3. pwdn swept from both 3v to 5v and 5v to 3v pwdn voltage volts 0 3.0 3.5 device current ma 4.0 4.5 5.0 5 10 15 20 25 30 35 40 45 figure 3. bias current vs. pwdn voltage to assure full power-down, the pwdn voltage should be within 0.5 v of the supply voltage at vpos. normal operation requires that the pwdn pin be taken at least 1.5 v below the supply voltage. the pwdn pin sources about 100 a when pulled to gnd (refer to pin function descriptions). it is not advisable to leave the pin floating when the device is to be disabled; a resis- tive pull-up to vpos is the minimum suggestion. the AD8343 requires about 2.5 s to turn off when pwdn is asserted; turn on time is about 500 ns. figures 4 and 5 show typical characteristics (they will vary with bypass component values). figure 6 shows the test configuration used to acquire these waveforms. 2 200nv 1.00v ch2 m 500ns ch2 4.48v 1 ch1 figure 4. pwdn response time device on to off 2 200nv 1.00v ch2 m 100ns ch2 4.48v 1 ch1 figure 5. pwdn response time device off to on 1nh 0.1 f vpos 0.1 f 14 13 12 11 10 9 8 1 2 3 4 5 6 7 comm AD8343 inpp inpm dcpl vpos pwdn comm comm outp outm comm loip loim comm matching network and transformer transformer hp8130 pulse generator hp8648c signal generator tektronix tds694c oscilloscope rf input 1740mhz if output 170mhz lo input 1570mhz matching network and transformer hp8648c signal generator trigger 8
3 &: %% 9 ac interfaces because of the AD8343 s wideband design, there are several points to consider in its ac implementation; the basic ac signal c onnection diagram shown in figure 7 summarizes these points. the input signal undergoes a single-ended-to- differential conversion and is then reactively matched to the impedance presented by the emitters of the core. the matching network also provides bias currents to these emitters. similarly, the lo input undergoes a single-ended-to-differential transfor- mation before it is applied to the 50 ? differential lo port. the differential output signal currents appear at high-impedance collectors and may be reactively matched and converted to a single-ended signal.
C14C rev. a AD8343 single-ended- to-differential conversion input matching network core bias network single-ended- to-differential conversion single-ended input signal single-ended lo input signal bias cell core AD8343 vpos dcpl pwdn loip loim inpp inpm outm outp comm lo driver single-ended output signal output matching network core bias network differential- to- single-ended conversion figure 7. basic ac signal connection diagram input interface (inpp and inpm) single-ended-to-differential conversion the AD8343 is designed to accept differential input signals for best performance. while a single-ended input can be applied, the signal capacity is reduced by 6 db. furthermore, there would be no cancellation of even-order distortion arising from the nonlin- ear input impedances, so the effective signal handling capacity will be reduced even further in distortion-sensitive situations. that is, the intermodulation intercepts are degraded. for these reasons it is strongly recommended that differential signals be presented to the AD8343 s input. in addition to commercially available baluns, there are various discrete and printed circuit elements that can produce the required balanced waveforms and impedance match (i.e., rat-race baluns). these alternate circuits can be employed to further reduce the component cost of the m ixer. baluns implemented in transmission line form (also known as common-mode chokes) are useful up to frequencies of around 1 ghz, but are often excessively lossy at the highest frequencies that the AD8343 can handle. m/a-com manufactures these baluns with their etc line. murata produces a true surface- mount balun with their ldb20c series. coilcraft and toko are also manufacturers of rf baluns. input matching considerations the design of the input matching network should be undertaken with two goals in mind: matching the source impedance to the input impedance of the AD8343 and providing a dc bias current path for the bias setting resistors. the maximum power transfer into the device will occur when there is a conjugate impedance match between the signal source and the input of the AD8343. this match can be achieved with the differential equivalent of the classic l network, as illustrated in figure 8. the figure gives two examples of the transformation from a single-ended l network to its differential counterpart. the design of l matching networks is adequately covered in texts on rf amplifier design (for example: microwave transis- tor amplifiers by guillermo gonzalez). l1 c1 l1/2 c1 l1/2 c2 l2 l2 2c2 2c2 single-ended differential figure 8. single-ended-to-differential transformation figure 9 shows the differential input impedance of the AD8343 at the pins of the device. the two measurements shown in the figure are for two different core currents set by resistors r3 and r4; the real value impedance shift is caused by the change in tran- sistor r e due to the change in current. the standard s parameter files are available at the adi website (www.analog.com). frequency (50mhz 2500mhz) 50mhz 500mhz 1000mhz 1500mhz 2500mhz 134 68 figure 9. input differential impedance (inpp, inpm) for two values of r3 and r4 figure 9 provides a reasonable starting point for the design of the network. however, the particular board traces and pads will transform the input impedance at frequencies in excess of about 500 mhz. for this reason it is best to make a differential input impedance measurement at the board location where the match- ing network will be installed, as a starting point for designing an accurate matching network. differential impedance measurement is made relatively easy using a technique presented in an article by lutz konstroffer in rf design , january 1999, entitled finding the reflection coeffi cient of a differential one-port device. this article presents a mathematical formula for converting from a two-port single- ended measurement to differential impedance. a full two-port measurement is p erformed using a vector network analyzer with port 1 and port 2 connected to the two differential inputs of the device at the desired measurement plane. the two-port measurement results are then processed with konstroffer s formula (following), which is straightforward and can be implemented through most rf design packages that can read and analyze network analyzer data. s ss s s ss s s sss sss = ? () ?? () +? ? () +? () ? () ?? () +? ? () + () 2 11 21 1 22 12 1 11 21 1 22 2 12 2 21 1 22 12 1 11 21 1 22
rev. a AD8343 C15C this measurement can also be made using the atn 4000 series multiport network analyzer. this instrument, and accompa- nying software, is capable of directly producing differential measurements. at low frequencies and i o = 16 ma, the differential input imped- ance seen at ports inpp and inpm of the AD8343 is low (~5 ? in series with parasitic inductances that total about 3 nh). because of this low value of impedance, it may be beneficial to choose a transformer-type balun that can also perform all or part of the real value impedance transformation. the turns ratio of the transformer will remove some of the matching burden from the differential l network and potentially lead to wider bandwidth. at frequencies above 1 ghz, the real part of the input imped- ance rises markedly and it becomes more attractive to use a 1:1 balun and rely on the l network for the entire impedance transformation. in order to obtain the lowest distortion, the inputs of the ad 8343 should be driven through external ballast resistors. at low fre quen- cies (up to perhaps 200 mhz) about 5 ? per side is appropriate; above about 400 mhz, 10 ? per side is better. the specified rf performance values for the AD8343 apply with these ballast resistors in use. these resistors improve linearity because their linear ac voltage drop partially swamps the nonlinear voltage swing occurring on the emitters. in cases where the use of a lossy balun is unavoidable, it may be worthwhile to perform simultaneous matching on both the input and output sides of the balun. the idea is to independently characterize the balun as a two-port device and then arrange a simultaneous conjugate match for it. unfortunately there seems to be no good way to determine the benefit this approach may offer in any particular case; it remains necessary to characterize the balun and then design and simulate appropriate matching networks to make an optimal decision. one indication that such effort may be worthwhile is the discovery that the adjustment of a post-balun-only matching network for best gain, differs apprecia- bly from that which produces best return loss at the balun s input. a better tactic may be to try a different approach for the balun, either purchasing a different balun or designing a discrete network. for more information on performing the input match, see a step-by-step approach to impedance matching in the section covering the AD8343 evaluation board, available from analog devices, inc. input biasing considerations the mixer core bias current of the AD8343 is adjustable from less than 5 ma to a safe maximum of 20 ma. it is important to note that the reliability of the AD8343 will be compromised for core currents set to higher than 20 ma. the AD8343 is tested to ensure that a value of 68.1 ? 1% will ensure safe operation. higher operating currents will reduce distortion and affect gain, noise figure, and input impedance (figures 10 and 11). as the quiescent current is increased by a factor of n the real part of the input impedance decreases by n. assuming that a match is maintained, the signal current increases by n , but the signal voltage decreases by n , which exercises a smaller portion of the nonlinear v C i characteristic of the common base connected mixer core transistors and results in lower distortion. r3/r4 0 20 conversion gain and noise figure db 16 12 8 4 200 100 120 60 80 40 140 160 180 90 80 70 60 50 40 30 20 10 0 input rf = 900mhz output if = 170mhz lo low side injection noise figure gain total supply current total supply current ma 20 100 figure 10. effect of r3/r4 value on gain and noise figure r3 and r4 0 20 input ip3 dbm and p1db dbm 20 15 10 5 200 100 120 60 80 40 140 160 180 90 80 70 60 50 40 30 20 10 0 input rf = 900mhz output if = 170mhz lo low side injection input ip3 p1db total supply current total supply current ma 25 figure 11. effect of r3/r4 value on input ip3 and gain compression at low frequencies where the magnitude of the complex input impedance is much smaller than the bias resistor values, adequate biasing can be achieved simply by connecting a resistor from each input to gnd. the input terminals are internally biased at 1.2 v dc (nominal), so each resistor should have a resistance value calculated as r bias = 1.2/i bias . the resistor values should be well matched in order to maintain full lo to output isolation; 1% toler- ance resistors are recommended. at higher frequencies where the input impedance of the AD8343 rises, it is beneficial to insert an inductor in series between each bias resistor and the corresponding input pin in order to minimize signal shunting (figure 24). practical considerations will limit the inductive reactance to a few hundred ohms. the best overall choice of inductor will be that value which places the self-resonant frequency at about the upper end of the desired input frequency range. note that there is an rf stability concern that argues in favor of erring on the side of too small an inductor value; reference section on input and output stability considerations. the murata lqw1608a series of inductors (0603 smt package) offers values up to 56 nh before the self-resonant frequency falls below 2.4 ghz. for optimal lo-to-output isolation it is important not to connect the dc nodes of the emitter bias inductors together in an attempt to share a single bias resistor. doing so will cause isolation degra- dation arising from v be mismatches of the transistors in the core.
C16C rev. a AD8343 output interface (outp, outm) the output of the AD8343 comprises a balanced pair of open- collector outputs. these should be biased to about the same voltage as is connected to vpos (see dc specifications table). connecting them to an appreciably higher voltage is likely to result in conduction of the esd protection network on signal peaks, which would cause high distortion levels. on the other hand, setting the dc level of the outputs too low is also likely to result in poor device linearity due to collector-base capacitance modulation or saturation of the core transistors. output matching considerations the AD8343 requires a differential load for much the same reasons that the input needs a differential source to achieve optimal device performance. in addition, a differential load will provide the best lo to output isolation and the best input to output isolation. at low output frequencies it is usually not appropriate to arrange a conjugate match between the device output and the load, even though doing so would maximize the small signal conversion gain. this is because the output impedance at low frequencies is quite high (a high resistance in parallel with a small capacitance). refer to figure 12 for a plot of the differential output impedance mea- sured at the device pins. this data is available in standard file format at the adi website (www.analog.com). if a matching high impedance load is used, sufficient output voltage swing will occur to cause output clipping even at rela tively low input levels, which constitutes a loss of dynamic range. the linear range of voltage swing at each output pin is about 1 v from the supply voltage vpos. a good compromise is to provide a load impedance of about 500 ? between the output pins at the desired output frequency (based on 15 ma to 20 ma bias current at each input). at output frequencies below 500 m hz, more output power can be obtained before the onset of gross clipping by using a lower load impedance; however, both gain and low order distor- tion performance will be degraded. 500mhz 1000mhz 1500mhz 2000mhz 50mhz frequency (50mhz 2500mhz) figure 12. output differential impedance (outp, outm) the output load impedance should also be kept reasonably low at the image frequency to avoid developing appreciable extra voltage swing, which would again reduce dynamic range. if maintaining a good output return loss is not required, a 10:1 (impedance) flux-coupled transformer may be used to present a suitable load to the device and to provide collector bias via a center tap as shown in figure 21. at all but the lowest output frequen- cies it becomes desirable to tune out the output capacitance of the AD8343 by connecting an inductor between the output pins. on the other hand, when a good output return loss is desired, the output may be resistively loaded with a shunt resistance between the output pins in order to set the real value of output impedance. with selection of both the transformer s impedance ratio and the shunting resistance as required, the desired total load (~500 ? ) will be achieved while optimizing both signal transfer and output return loss. at higher output frequencies the output conductance of the device becomes higher (figure 12), with the consequence that above about 900 mhz it does become appropriate to perform a conjugate match between the load and the AD8343 s output. the device s own output admittance becomes sufficient to remove the threat of clipping from excessive voltage swing. just as for the input, it may become necessary to perform differential output impedance measurements on your board layout to effectively develop a good matching network. output biasing considerations when the output single-ended-to-differential conversion takes the form of a transformer whose primary winding is center- tapped, simply apply vpos to the tap, preferably through a ferrite bead in series with the tap in order to avoid a common- mode instability problem (reference section on input and output stability considerations). refer to figure 21 for an example of this network. the collector dc bias voltage should be nominally equal to the supply voltage applied to pin 5 (vpos). if a 1:1 transmission line balun is used for the output, it will be necessary to bring in collector bias through separate inductors. these inductors should be chosen to obtain a high impedance at the rf frequency, while maintaining a suitable self-resonant frequency. refer to figure 22 for an example of this network. input and output stability considerations the differential configuration of the input and output ports of the AD8343 raises the need to consider both differential and common-mode rf stability of the device. throughout the fol- lowing stability discussion, common mode will be used to refer to a signal that is referenced to ground. the equivalent common- mode impedance will be the value of impedance seen from the node under discussion to ground. the book, microwave transistor amplifiers by guillermo gonzalez also has an excellent section covering stability of amplifiers. the AD8343 is unconditionally stable for any differential imped- ance, so device stability need not be considered with respect to the differential terminations. however, the device is potentially unstable (k factor is less than one) for some common-mode impedances. figures 13 and 14 plot the input and output common-mode stability regions, respectively. figure 15 shows the test equipment configu- ration to m easure these stability circles. the plotted stability circles in figure 14 indicate that the guiding principle for preventing stability problems due to common-mode output loading is to avoid high-q common-mode inductive loading. this stability concern is of particular importance when the output is taken from the device with a center-tapped transformer. the common-mode inductance to the center tap, which arises from imperfect coupling between the halves of the primary winding, produces an unstable common-mode loading condition. fortu- nately, there is a simple solution: insert a ferrite bead in series with
rev. a AD8343 C17C the center tap, then provide effective rf bypassing on the power supply side of the bead. the bead should develop substantial imped- ance (tens of ohms) by the time a frequency of about 200 mhz is reached. the murata blm21p300s is a possible choice for many applications. 50mhz 150mhz frequency: 50mhz to 2500mhz increment: 100mhz figure 13. common-mode input stability circles 150mhz 50mhz frequency: 50mhz to 2500mhz increment: 100mhz figure 14. common-mode output stability circles 1nh 0.1 f vpos hp8753c network analyzer atn-4111b s parameter test set hp-ib atn-4000 series multiport test system 0.1 f 14 13 12 11 10 9 8 1 2 3 4 5 6 7 comm AD8343 inpp inpm dcpl vpos pwdn comm comm outp outm comm loip loim comm bias tee bias tee bias tee bias tee figure 15. impedance and stability circle test schematic in cases where a transmission line balun is used at the output, the solution needs more exploration. after the differential imped- ance matching network is designed, it is possible to mea sure or simulate the common-mode impedance seen by the device. this impedance should be plotted against the stability circles to ensure stable operation. an alternate topology for the matching network may be required if the proposed network produces an unacceptable common-mode impedance. for the device input, capacitive common-mode loading produces an unstable circuit, particularly at low frequencies (figure 13). fortunately, either type of single-ended-to-differential conversion (transmission line balun or flux-coupled transformer) tends to produce inductive loading, although some matching network topologies and/or component values could circumvent this desirable behavior. in general, a simulation of the common-mode termination seen by the AD8343 s input port should be plotted against the input stability circles to check stability. this is especially recommended if the single-ended-to-differential conversion is done with a discrete component circuit. local oscillator input interface (loip, loim) the lo terminals of the AD8343 are internally biased; connec- tions to these terminals should include dc blocks, except as noted below in the dc coupling the lo section. the differential lo input return loss (with a 50 ? differential input impedance) is presented in figure 16. as shown, this port has a typical differential return loss of better than 9.5 db (2:1 vswr). if better return loss is desired for this port, differ- ential matching techniques can also be applied.
C18C rev. a AD8343 frequency ( 50mhz 2500mhz ) 0 30 0 500 return loss db 1000 1500 2000 2500 25 20 15 10 5 figure 16. lo input differential return loss at low lo frequencies, it is reasonable to drive the AD8343 with a single-ended lo, connecting the undriven terminal to gnd through a dc block. this will result in an input impedance closer to 25 ? at low frequencies, which should be factored into the design. at higher lo frequencies, differential drive is recomm ended. the suggested minimum lo power level is about C 12 dbm. this can be seen in figure 17. lo power dbm 0 40 conversion gain db 4 3 2 1 20 10 30 25 20 15 10 5 noise figure 0 noise figure db 5 conversion gain input rf = 900mhz output if = 170mhz lo low side injection figure 17. gain and noise figure vs. lo input power dc coupling the lo the AD8343 s lo limiting amplifier chain is internally dc-coupled. in some applications or experimental situations it is useful to exploit this property. this section addresses some ways in which to do it. the lo pins are internally biased at about 360 mv with respect to comm. driving the lo to either extreme requires injecting several hundred microamps into one lo pin and extracting about the same amount of current from the other. the incremental impedance at each pin is about 25 ? , so the voltage level on each pin is disturbed very little by the application of external currents in that range. figure 18 illustrates how to drive the lo port with continuous dc and also from standard ecl powered by C 5.2 v. ecl bias AD8343 vpos dcpl pwdn loip loim inpp inpm outm outp comm lo driver 5.2v 5.2v 390 1.2k 1.2k 390 3.6k 3.6k +5v 5.2v ecl 13k continuous dc 1k bias AD8343 vpos dcpl pwdn loip loim inpp inpm outm outp comm lo driver figure 18. dc interface to lo port a step-by-step approach to impedance matching the following discussion addresses, in detail, the matter of establishing a differential impedance match to the AD8343. this section will specifically deal with the input match, and using side a of the evaluation board (figure 23). an analo- gous procedure would be used to establish a match to the output if desired. step 1: circuit setup in order to do this work the AD8343 must be powered up, driven with lo; its outputs should be terminated in a manner that avoids the common-mode stability problem as discussed in the input and output stability section. a convenient way to deal with the output termination is to place ferrite chokes at l3a and l4a and omit the output matching components altogether. it is also important to establish the means of providing bias currents to the input pins because this network may have unexpected loading effects and inhibit matching progress. step 2: establish target impedance this step is necessary w hen the single-ended-to-differential network (input balun) does not produce a 50 ? output imped- ance. in order to provide for maximum power transfer, the input impedance of the matching network, loaded with the AD8343 input impedance (including ballast resistors), should be the conju- gate of the output impedance of the single-ended-to-differ ential network. this step is of particular importance when utilizing transmission line baluns because the differential output imped- ance of the input balun may differ significantly from what is expected. therefore, it is a good idea to make a separate mea- surement of this impedance at the desired operating frequency before proceeding with the matching of the AD8343. the idea is to make a differential measurement at the output of the balun, with the single-ended port of the balun terminated in 50 ? . again, there are two methods available for making this measurement: use of the atn multiport network analyzer to
rev. a AD8343 C19C measure the differential impedance directly, or use of a standard two-port network analyzer and konstroffer s transformation equation. in order to utilize a standard two-port analyzer, connect the two ports of the calibrated vector network analyzer (vna) to the bal- anced output pins of the balun, measure the two-port s parameters, then use konstroffer s formula to convert the two-port param- eters to one-port differential . s ss s s ss s s sss sss = ? () ?? () +? ? () +? () ? () ?? () +? ? () + () 2 11 21 1 22 12 1 11 21 1 22 2 12 2 21 1 22 12 1 11 21 1 22 step 3: measure AD8343 differential impedance at location of first matching component once the target impedance is established, the next step in match- ing to the AD8343 is to measure the differential impedance at the location of the first matching component. the a side of the evaluation board is designed to facilitate doing so. before doing the board measurements, it is necessary to perform a full two-port calibration of the vna at the ends of the cables that will be used to connect to the board s input connectors, using the solt (short, open, load, thru) method or equivalent. it is a good idea to set the vna s sweep span to a few hundred mhz or more for this work because it is often useful to see what the circuit is doing over a large range of frequencies, not just at the intended operating frequency. this is particularly useful for detecting stability problems. after the calibration is completed, connect network analyzer ports one and two to the differential inputs of the AD8343 evaluation board. on the AD8343 evaluation board, it is necessary to temporarily install jumpers at z1a and z3a if z4a is the desired component location. zero ohm resistors or capacitors of sufficient value to exhibit negligible reactance work nicely for this purpose. next, extend the reference plane to the location of your first match- ing component. this is accomplished by solidly shorting both pads at the component location to gnd ( note: power to the board must be off for this operation! ) adjust the vna reference plane extensions to make the entire trace collapse to a point (or best approximation thereof near the desired frequency) at the zero impedance point of the smith chart. do this for each port. a reasonable way to provide a good rf short is to solder a piece of thin copper or brass sheet on edge across the pads to the nearby gnd pads. now, remove the short, apply power to the board, and take readings. take a look at both s11 and s22 to verify that they remain inside the unit circle of the smith chart over the whole frequency range being swept. if they fail to do so, this is a sign that the device is unstable (perhaps due to an inappropriate common-mode load) or that the network analyzer calibration is wrong. either way the problem must be addressed before proceeding further. assuming that the values look reasonable, use konstroffer s formula to convert to differential . step 4: design the matching network the next step is to perform a trial design of a matching network utilizing standard impedance matching techniques. the network may be designed using single-ended network values, then con- verted to differential form as illustrated in figure 8. figure 19 shows a theoretical design of a series c/shunt c l network applied between 50 ? and a typical load at 1.8 ghz. 0.2 0.5 1.0 2.9pf shunt capacitor 5.0 figure 19. theoretical design of matching network this theoretical design is important because it establishes the basic topology and the initial matching value for the network. the theoretical value of 2.9 pf for the initial matching com- ponent is not available in standard capacitor values, so a 3.0 pf is placed in the first shunt matching location. this value may prove to be too large, causing an overshoot of the 50 ? real imped- ance circle, or too small, causing the opposite effect. alw ays keep in mind that this is a measure of differential impedance. the value of the capacitor should be modified to achieve the desired 50 ? real impedance. however, it may occasionally happen that the inserted shunt capacitor moves the impedance in completely unexpected and undesired ways. this is almost always an indication that the reference plane was improperly extended for the measurement. the user should readjust the reference planes and attempt the shunt capacitor match with another calculated value. when a differential impedance of 50 ? (real part) is achieved, the board should be deenergized and another short placed on the board in preparation for resetting the port extensions to a new reference plane location. this short should be placed where next the series components are expected to be added, and it is important that both ports one and two be extended to this point on the board. another differential measurement must be taken at this point to establish the starting impedance value for the next matching component. note that if 50 ? pcb traces of finite length are used to connect pads, the impedance will experience an angular rotation to another location on the smith chart as indicated in figure 20.
C20C rev. a AD8343 0.2 0.5 1.0 5.0 2.0 0.2 0.5 1.0 2.0 5.0 0 3.3pf shunt capacitor 5mm 50 trace frequency = 1.8ghz figure 20. effect of 50 ? pcb trace on 50 ? real impedance load with the reference plane extended to the location of the series matching components, it may now be necessary to readjust the shunt capacitance value to achieve the desired 50 ? real imped- ance. however, this rotation will not be very noticeable if the board traces are fairly short or the application frequency is low. as before, calculate the series capacitance value required to move in the direction shown as step two in figure 19, choose the nearest standard component remembering to perform the differential conver- sion, and install on the board. again, if any unexpected impedance transformations occur the reference planes were probably extended incorrectly making it necessary to readjust these planes. this value of series capacitance should be adjusted to obtain the desired value of differential impedance. the above steps may be applied to any of the previously dis- cussed matching topologies suitable for the AD8343. also, if a non 50 ? target impedance is required, simply calculate and adjust the components to obtain the desired load impedance. caution: if the matching network topology requires a differen- tial shunt inductor between the inputs, it may be necessary to place a series blocking capacitor of low reactance in series with the inductor to avoid creating a low resistance dc path between the input terminals of the AD8343. failure to heed this warning will result in very poor lo-output isolation step 5: transfer the matching network to the final design on the b side of the AD8343 evaluation board, install the match- ing network and the input balun. install the same output network as used for the work on the a side, then power up the board and measure the input return loss at the rf input connector on the board. strictly speaking, the above procedure (if carried out accurately) for matching the AD8343 will obtain the best conver- sion gain; this may differ materially from the condition which results in best return loss at the board s input if the balun is lossy. if the result is not as expected, the balun is probably producing an unexpected impedance transformation. if the performance is extremely far from the desired result and it was assumed that the output impedance of the balun was 50 ? , it may be necessary to measure the output impedance of the balun in question. the design process should be repeated using the balun s output imped- ance instead of 50 ? as the target. however, if the perform ance is close to the desired result it should be possible to tweak the values of the matching network to achieve a satisfactory o utcome. these changes should begin with a change from one standard value to the adjacent standard value. with these minor modi- fications to the matching network, one is able to evaluate the trend required to reach the desired result. if the result is unsatisfactory and an acceptable compromise cannot be reached by further adjustment of the matching network, there are two options: obtain a better balun, or attempt a simultaneous conjugate match to both ports of the balun. accomplishing the latter (or even evaluating the prospects for useful improvement) requires obtaining full two-port, single-ended-to-differential s parameters for the balun, which requires the use of the atn 4000 or similar multiport network analyzer test set. gonzalez presents formulas for calculating the simultaneous conjugate match in the section entitled, simultaneous conjugate match: bilateral case in his book, microwave transistor amplifiers. at higher frequencies the measurement process described above becomes increasingly corrupted by unaccounted for impedance transformations occurring in the traces and pads between the input connectors and the extended reference plane. one approach to dealing with this problem is to access the desired measurement points by soldering down semirigid coax cables that have been conn ected to the vna and directly calibrated at the free ends. applications downconverting mixer a typical downconversion application is shown in figure 21 with the AD8343 connected as a receive mixer. the input single-ended-to-differential conversion is obtained through the use of a 1:1 transmission line balun. the input matching network is positioned between the balun and the input pins, while the output is taken directly from a 4:1 impedance ratio (2:1 turns ratio) transformer. the local oscillator signal at a level of C 12 dbm to C 3 dbm is brought in through a second 1:1 balun. lo in 10dbm 1:1 v pos 4.71 0.1 f AD8343 vpos dcpl pwdn loip loim inpp inpm outm outp comm if out fb 4:1 bias v pos r1 a 68 l1 a l1 b r1 b 68 r fin z1 z2 a z2 b ferrite bead 1:1 figure 21. typical downconversion application
rev. a AD8343 C21C r1a and r1b set the core bias current of 18.5 ma per side. l1a and l1b provide the rf choking required to avoid shunting the signal. z1, z2a, and z2b comprise a typical input matching net- work that is designed to match the AD8343 s differential input impedance to the differential output impedance of the balun. the if output is taken through a 4:1 (impedance ratio) trans- former that reflects a 200 ? differential load to the collectors. this output coupling arrangement is reasonably broadband, although in some cases the user might want to consider adding a resonator tank circuit between the collectors to provide a mea- sure of if selectivity. the ferrite bead (fb), in series with the output transformer s center tap, addresses the common-mode stability concern. in this circuit the pwdn pin is shown connected to gnd, which enables the mixer. in order to enter power-down mode and conserve power, the pwdn pin should be taken within 500 mv of vpos. the dcpl pin should be bypassed to gnd with about 0.1 f. failure to do so could result in a higher noise level at the output of the device. upconverting mixer a typical upconversion application is shown in figure 22. both the input and output single-ended-to-differential conversions are obtained through the use of 1:1 transmission line baluns. the differential input and output matching networks are designed between the balun and the i/o pins of the AD8343. the local oscillator signal at a level of C 12 dbm to C 3 dbm is brought in through a third 1:1 balun. r1a and r1b set the core bias current of 18.5 ma per side. z1, z2a, and z2b comprise a typical input matching network that is designed to match the AD8343 s differential input impedance to the differential output impedance of the balun. it was assumed for this example that the input frequency is low and that the magnitude of the device s input impedance is therefore much smaller than the bias resistor values, allowing the input bias inductors to be eliminated with very little penalty in gain or noise performance. in this example, the output signal is taken via a differential matching network comprising z3 and z4a/b, then through the 1:1 balun and dc blocking capacitors to the single-ended output. the output frequency is assumed to be high enough that conju- gate matching to the output of the AD8343 is desirable, so the goal of the matching network is to provide a conjugate match between the device s output and the differential input of the output balun. this circuit uses shunt feed to provide collector bias for the transistors because the output balun in this circuit has no con- venient center-tap. the ferrite beads, in series with the output s bias inductors, provide some small degree of damping to ease the common-mode stability problem. unfortunately this type of output balun may present a common-mode load that enters the region of output instability, so most of the burden of avoiding overt instability falls on the input circuit, which should present an inductive common-mode termination over as broad a band of frequencies as possible. the pwdn pin is shown as tied to gnd, which enables the mixer. the dcpl pin should be bypassed to gnd with about 0.1 f to bypass noise from the internal bias circuit. rf out r1 a r fin r1 b 0.1 f v pos lo in v pos 0.1 f AD8343 vpos dcpl pwdn loip loim inpp inpm outm outp comm bias v pos z2 a z2 b 0.1 f 0.1 f z1 fb z3 z4 a fb z4 b figure 22. typical upconversion application
C22C rev. a AD8343 evaluation board the AD8343 evaluation board has two independent areas, denoted a and b. the circuit schematics are shown in figures 23 and 24. an assembly drawing is included in figure 25 to ease identification of components, and representations of the board layout are included in figures 26 through 29. the a region is configured for ease in making device impedance measurements as part of the process of developing suitable matching networks for a final application. the b region is designed for operating the AD8343 in a single-ended application environment and therefore includes pads for attaching baluns or transformers at both the input and output. the following tables (iii through v) delineate the components used for the characterization procedure used to generate tpc 1 through 42 and most other data contained in this data sheet. table iii lists the support components that are delivered with the AD8343 evaluation board. note that the board is shipped without any frequency specific components installed. table iv lists the com- ponents used to ob tain the frequency selection necessary for the product receiver evaluation, and table v lists the transmitter evaluation components. table iii. values of support components shipped with evaluation board and used for device characterization component designator value quantity part number c1a, c1b, c3a, c3b, c11a, c11b 0.1 f 6 murata grm40z5u104m50v c2a, c2b, c4a, c4b, c5a, c5b, c6a, c6b, c9a, 0.01 f 16 murata grm40x7r103k50v c9b, c10a, c10b, c12a, c12b, c13a, c13b r3a, r3b, r4a, r4b 68.1 ? 1% 4 panasonic erj6enf68r1v (t and r packaging) r1a, r1b, r2a, r2b 3.9 ? 5% 4 panasonic erj6geyj3r9v (t and r packaging) r5a, r5b 0 ? 2 panasonic erj6geyjr00v (t and r packaging) j1a, j1b ferrite bead 2 murata blm21p300s (2.0 mm smt) t1a, t1b, t2b (various) 1:1 3 m/a-com etc1-1-13 wideband balun * t3b (various) 4:1 1 mini-circuits tc4-1w transformer r6a, r6b, r7a, r7b 10 ? 1% 4 panasonic erj6geyj100v (t and r packaging) l1a, l1b, l2a, l2b 56 nh 4 panasonic elj-re56njf3 table iv. values of matching components used for receiver characterization component designator value quantity part number f in = 400 mhz, f out = 70 mhz t1b, t2b 1:1 2 m/a-com etc1-1-13 wideband balun * t3b 4:1 1 mini-circuits tc4-1w transformer r6b, r7b 10 ? 2 panasonic erj6geyj100v (t and r packaging) z1b, z3b jumper 2 #30 awg wire across pads z2b 8.2 pf 1 murata ma188r2j z5b, z7b 150 nh 2 murata lqw1608ar15g00 z6b 3.4 pf 1 murata ma182r4b || ma181r0b l1b, l2b 56 nh 2 panasonic elj-re56njf3 z4b, z8b, l3b, l4b, z9b not populated f in = 900 mhz, f out = 170 mhz t1b, t2b 1:1 2 m/a-com etc1-1-13 wideband balun * t3b 4:1 1 mini-circuits tc4-1w transformer r6b, r7b 10 ? 2 panasonic erj6geyj100v (t and r packaging) z1b, z3b jumper 2 #30 awg wire across pads z4b 3.0 pf 1 murata grm39c0g3r0b50v z5b, z7b 120 nh 2 murata lqw1608ar12g00 z6b 0.4 pf 1 murata ma180r4b l1b, l2b 56 nh 2 panasonic elj-re56njf3 z2b, z8b, l3b, l4b, z9b not populated f in = 1900 mhz, f out = 425 mhz t1b, t2b 1:1 3 m/a-com etc1-1-13 wideband balun * t3b 4:1 1 mini-circuits tc4-1w transformer r6b, r7b 10 ? 2 panasonic erj6geyj100v (t and r packaging) z1b, z3b 6.8 nh 2 murata lqw1608a6n8c00 z2b 0.6 pf 1 murata ma180r6b z5b, z7b 39 nh 2 murata lqw1608a39ng00 z8b 2.0 pf 1 murata ma182r0b l1b, l2b 56 nh 2 panasonic elj-re56njf3 z6b, z4b, l3b, l4b, z9b not populated
rev. a AD8343 C23C table iv. values of matching components used for receiver characterization (continued) component designator value quantity part number f in = 1900 mhz, f out = 170 mhz t1b, t2b 1:1 2 m/a-com etc1-1-13 wideband balun * t3b 4:1 1 mini-circuits tc4-1w transformer r6b, r7b 10 ? 2 panasonic erj6geyj100v (t and r packaging) z1b, z3b 6.8 nh 2 murata lqw1608a6n8c00 z4b 0.5 pf 1 murata ma180r5b z5b, z7b 100 nh 2 murata lqw1608ar10g00 z6b 2.4 pf 1 murata ma182r4b l1b, l2b 56 nh 2 panasonic elj-re56njf3 z2b, z8b, l3b, l4b, z9b not populate d table v. values of matching components used for transmitter characterization component designator value quantity part number f in = 150 mhz, f out = 900 mhz t1b, t3b 1:1 2 m/a-com etc1-1-13 wideband balun * t2b 1:1 1 mini-circuits adtl1-18-75 r6b, r7b 5.1 ? 2 panasonic erj6geyj510v (t and r packaging) z1b, z3b 8.2 nh 2 murata lqw1608a8n2c00 z2b 33 pf 1 murata grm39c0g330j100v z5b, z7b 8.2 nh 2 murata lqg11a8n2j00 z8b 6.2 pf 1 murata ma186r2c l1b, l2b 56 nh 2 panasonic elj-re56njf3 l3b, l4b 150 nh 2 murata lqw1608ar15g00 z4b, z6b, z9b not populated f in = 150 mhz, f out = 1900 mhz t1b, t3b 1:1 2 m/a-com etc1-1-13 wideband balun * t2b 1:1 1 mini-circuits adtl1-18-75 r6b, r7b 5.1 ? 2 panasonic erj6geyj510v (t and r packaging) z1b, z3b 8.2 nh 2 murata lqg11a8n2j00 z2b 33 pf 1 murata grm39c0g330j100v z5b, z7b 1.8 nh 2 murata lqg11a1n8s00 z8b 1.8 pf 1 murata ma181r8b l1b, l2b 56 nh 2 panasonic elj-re56njf3 l3b, l4b 68 nh 2 murata lqw1608a68ng00 z4b, z6b, z9b not populated * the ect1-1-13 wideband balun was chosen for ease in customer s independent evaluation. these baluns are quite acceptable for use as t1 on the lo port, but may not be acceptable for use as t2 on the high-performance rf input. it has been found that board to board performance variations become unacceptable when this balun is used at higher (> 500 mhz) frequencies. a narrow-band balun is suggested for this critical interface. refer to the device interfaces and a step-by-step approach to impedance matching section of this document for more information.
C24C rev. a AD8343 l2a vpos_a gnd_a pwdn_1_a input_p_a input_m_a pwdn_a l1a r3a r4a r5a c5a z1a z2a z4a r1a c1a c2a j1a z7a z5a z9a z8a c9a c10a l4a c8a c12a c13a t1a l3a c7a output_p_a output_m_a lo input_a 14 13 12 11 10 9 8 1 2 3 4 5 6 7 comm AD8343 inpp inpm dcpl vpos pwdn comm comm outp outm comm loip loim comm c11a duta z3a c6a r2a c3a c4a 1 24 3 5 z9a r7a r9a reference table i for component values as shipped. reference table i, ii, and iii for characterization values. figure 23. characterization and evaluation board circuit a input_b t3b l2b vpos_b gnd_b pwdn_1_b pwdn_b l1b r3b r4b r5b c5b z1b z2b z4b r1b c1b c2b j1b z7b z5b z9b z8b c9b c10b l4b c8b c12b c13b t1b l3b c7b output_b lo_input_b 14 13 12 11 10 9 8 1 2 3 4 5 6 7 comm AD8343 inpp inpm dcpl vpos pwdn comm comm outp outm comm loip loim comm c11b dutb z3b c6b r2b c3b c4b 1 24 3 5 1 2 43 5 t2b 4 2 1 3 6 z9b r7b r9b reference table i for component values as shipped. reference table i, ii, and iii for characterization values. figure 24. characterization and evaluation board circuit b
rev. a AD8343 C25C assembly bottom assembly top figure 25. evaluation board assembly drawing figure 26. evaluation board artwork top figure 27. evaluation board artwork internal 1
C26C rev. a AD8343 figure 28. evaluation board artwork internal 2 figure 29. evaluation board artwork bottom
rev. a AD8343 C27C outline dimensions dimensions shown in inches and (mm). 14-lead plastic thin shrink small outline package (tssop) ru-14 14 8 7 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
C28C c01034C0C3/02 (a) printed in u.s.a. rev. a AD8343 revision history location page data sheet changed from rev.0 to rev. a. edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to input interface (loip, loim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edits to table iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 edits to table iv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 edits to table v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 edits to figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 edits to figure 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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